37C672 Datasheet, PDF (117/173 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH FAST IR

Enhanced Super I/O Controller with Fast IR
Datasheet
17.9 Port 92 Fast GATEA20 and Keyboard Reset
17.9.1 Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register
(Logical Device 7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
Name
Location
Default Value
Attribute
Size
Port 92
92h
24h
Read/Write
8 bits
PORT 92 REGISTER
BIT FUNCTION
7:6 Reserved. Returns 00 when read.
5 Reserved. Returns a 1 when read.
4 Reserved. Returns a 0 when read.
3 Reserved. Returns a 0 when read.
2 Reserved. Returns a 1 when read.
1 ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to
be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven
high.
0 Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU
to effect a mode switch from Protected Virtual Address Mode to the Real
Address Mode. This provides a faster means of reset than is provided by the
Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this
bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 µs
after a delay of 500 ns. Before another nALT_RST pulse can be generated,
this bit must be written back to a 0.
8042
P21
0
0
1
1
NGATEA20
ALT_A20
0
1
0
1
SYSTEM
NA20M
0
1
1
1
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control.
This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to
provide a software means of resetting the CPU. This provides a faster means of reset than is provided by
the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a
minimum of 6µs, after a delay of a minimum of 14µs. Before another nALT_RST pulse can be generated,
bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven
inactive high (bit 0 in the Port 92 Register is set to 0).
SMSC FDC37C672
Page 117
DATASHEET
Rev. 10-29-03