USB97C100 Datasheet, PDF (15/64 Pages) SMSC Corporation – Multi-Endpoint USB Peripheral Controller

MMU Block Register Summary
ADDRESS
0x6000
7F50
7F51
7F52
7F53
7F54
7F55
7F56
7F57
7F58
7F59
7F60
7F61
7F62
7F63
7F64
7F65
7F66
7F67
7F6E
7F6F
Table 7 - MMU Block Register Summary
NAME
R/W
DESCRIPTION
MMU REGISTERS
MMU_DATA
R/W
8051-MMU Data Window Register FIFO
PRL
R/W
8051-MMU Pointer Register (Low)
PRH
R/W
8051-MMU Pointer Register (High) & R/W
MMUTX_SEL
R/W
8051-MMU TX FIFO Select for Commands
MMUCR
W
8051-MMU Command Register
ARR
R
8051-MMU Allocation Result Register
PNR
R/W
8051-MMU Packet Number Register
PAGS_FREE
R/W
Pages Free In the MMU
TX_MGMT
R
TX Management Register 2
RXFIFO
R
RX Packet FIFO Register (All EPs)
POP_TX
R
POP TX FIFO
TXSTAT_A
R
TX Packet FIFO Status Register (EP0-3)
TXSTAT_B
R
TX Packet FIFO Status Register (EP4-7)
TXSTAT_C
R
TX Packet FIFO Status Register (EP8-11)
TXSTAT_D
R
TX Packet FIFO Status Register (EP12-15)
MMU_TESTx
N/A
Reserved for Test
MMU_TESTx
N/A
Reserved for Test
MMU_TESTx
N/A
Reserved for Test
TX_MGMT
R/W
TX Management Register 1
MMU_TESTx
N/A
Reserved for Test
MMU_TESTx
N/A
Reserved for Test
SMSC DS – USB97C100
Page 15
Rev. 01/03/2001