HC652 Datasheet, PDF (5/9 Pages) System Logic Semiconductor – Octal 3-State Bus Transceivers and D Flip-Flops

SL74HC652
TIMING REQUIREMENTS(Input t_r=t_f=6.0 ns)
Symbol
Parameter
V_CC
Guaranteed Limit
V 25 °C to-55°C ≤85°C ≤125°C Unit
t_su
Minimum Setup Time, Input A to
2.0
50
A-to-B Clock (or Input B to B-to-A
4.5
10
Clock) (Figure 7)
6.0
9
65
75
ns
13
15
11
13
t_h
Minimum Hold Time, A-to-B Clock to 2.0
25
Input A (or B-to-A Clock to
4.5
5
Input B) (Figure 7)
6.0
5
30
40
ns
6
8
5
7
t_w
Minimum Pulse Width, A-to-B Clock 2.0
75
(or B-to-A Clock)
4.5
15
(Figure 7)
6.0
13
95
110
ns
19
22
16
19
t_r, t_f Maximum Input Rise and Fall Times
2.0
1000
(Figures 2 and 3)
4.5
500
6.0
400
1000
1000
ns
500
500
400
400
TIMING DIAGRAM
SLS
System Logic
Semiconductor