HC652 Datasheet, PDF (4/9 Pages) System Logic Semiconductor – Octal 3-State Bus Transceivers and D Flip-Flops

SL74HC652
AC ELECTRICAL CHARACTERISTICS(C_L=50pF,Input t_r=t_f=6.0 ns)
Symbol
Parameter
V_CC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
t_PLH, t_PHL Maximum Propagation Delay, Input A to Output B 2.0 180
225
270
ns
(or Input B to Output A)
4.5 36
45
54
(Figures 2,3 and 9)
6.0 31
38
46
t_PLH, t_PHL
Maximum Propagation Delay, A-to-B Clock to
Output B (or B-to-A Clock to Output A)
(Figures 1 and 9)
2.0 240
300
360
ns
4.5 48
60
72
6.0 41
51
61
t_PLH, t_PHL Maximum Propagation Delay, A-to-B Source to
2.0 220
275
330
ns
Output B (or B-to-A Source to Output A) (Figures 4.5 44
55
66
4 and 9)
6.0 37
47
56
t_PLZ, t_PHZ Maximum Propagation Delay , Direction or Output 2.0 170
215
255
ns
Enable to Output A or B
4.5 34
43
51
(Figures 5,6 and 10)
6.0 29
37
43
t_PZL, t_PZH Maximum Propagation Delay , Direction or Output 2.0 180
225
270
ns
Enable to Output A or B
4.5 36
45
54
(Figures 5,6 and 10)
6.0 31
38
46
t_TLH, t_THL Maximum Output Transition Time, Any Output
2.0 60
75
90
ns
(Figure 2)
4.5 12
15
18
6.0 10
13
15
C_IN
Maximum Input Capacitance
C_OUT Maximum Three-State I/O Capacitance
(Output in High-Impedance State
-
10
10
10
pF
-
15
15
15
pF
Power Dissipation Capacitance (Per Channel)
C_PD Used to determine the no-load dynamic power
consumption:
P_D=C_PDV_CC2f+I_CCV_CC
Typical @25°C,V_CC=5.0 V
60
pF
SLS
System Logic
Semiconductor