SKY73208-11 Datasheet, PDF (5/17 Pages) Skyworks Solutions Inc. – 350-5000 MHz Wideband Receive Mixer with Integrated Integer-N PLL and VCO

Table 2. SPI Timing Requirements
t_period
t_high
t_su
t_hld
t_elch
t_width
t_efeh
Timing
Clock period
Clock high time
Data setup to clock rise
Data hold from clock rise
Enable low to clock rise
Enable high width
Clock fall to enable high
Description
DATA SHEET • SKY73208-11 MIXER WITH PLL AND VCO
Minimum Time
(ns)
25
10
5
5
10
10
20
CLK
t_period
t_high
DATA
t_su
t_hld
LE
t_elch
t_cfeh
t_width
S2434
Figure 4. SPI Input Timing Diagram
Serial Bus Timing
The SPI bus speed is programmable. Timing requirements for the
CLK, DATA, and LE signals are provided in Table 2. A serial data
input timing diagram is shown in Figure 4.
PLL Control Registers (R-Divider and N-Divider)
There are three digital PLL control registers that are used to store
the R-divider and N-divider values: R_DIV, N_DIV1, and N_DIV2.
By default, all registers are 25 bits wide. Bits[20:16] are the
address bits of the registers. The 16 least significant bits (LSBs)
represent the data bits.
Three values are needed to calculate the three PLL dividers: the
desired frequency (FRF), the VCO divider (D), and the frequency
step size (FSTEP).
The VCO frequency (FVCO) has a range of 2.8 GHz to 6.0 GHz, and
is defined by the product of the desired frequency (FRF) and the
VCO divider, D:
F_VCO  F_RF  D
(1)
The VCO divider (equal to 1, 2, 4, or 8) is chosen so that the
product of FRF × D is within the specified VCO range.
The frequency step size (FSTEP) is a user-defined value. Given
FSTEP and D, the comparison frequency (FCOMP) can be calculated
by:
F_COMP  F_STEP  D
(2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
201317F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 5, 2015
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