SKY73208-11 Datasheet, PDF (4/17 Pages) Skyworks Solutions Inc. – 350-5000 MHz Wideband Receive Mixer with Integrated Integer-N PLL and VCO

DATA SHEET • SKY73208-11: MIXER WITH PLL AND VCO
Charge Pump
The charge pump is used to convert the logic levels of the Up and
Dn pulses, carrying the phase error between the reference and
the divided signal into analog quantities/current pulses.
The output of the SKY73208-11 charge pump is programmable
and varies between 1.2 mA and 7.2 mA. Additional adjustment of
the charge pump current can be accomplished by changing the
value of the external PLL bias resistor.
Lock Detector
The lock detector circuit is activated when the phase difference
between the Up and Dn phase detector signals for a given number
of comparison cycles is shorter than a fixed delay. The CMOS
output is active high when the loop is locked. The lock detector
can be monitored from pin 1 (LD).
If single-ended input is required, one of the pins can be grounded
or an external balun can be used. The register settings to enable
this mode of operation are detailed in the Skyworks document,
Wideband, Integer-N Phase-Locked Loop Programming Guide,
document #201322.
LO Output
It is possible to monitor the LO signal (either the internally
generated LO or an externally applied LO) or route the signal to
another device that requires the same LO frequency. The
differential LO output is available at pins 19 and 20 (OUTBUFN
and OUTBUFP, respectively) using external coupling capacitors.
If single-ended output is desired, use pin 19 or an external balun.
This feature does not require any specific register bit setting and
these pins can be left floating if not used.
VCO
The VCO is designed to generate the LO signal with the tuning
function controlled by the synthesizer.
VCO Dividers and LO Chain
The divider chain consists of dividers and LO drivers.
The direct, non-divided VCO output can be monitored at the bi-
directional internal/external VCO pins 5 and 6 (EXT_VCO_INP and
EXT_VCO_INN, respectively). The divider chain and the internal
PLL can be locked by an external VCO.
External LO
The SKY73208-11 can accept an external LO signal and disable
the internal synthesizer. The high impedance differential injection
port is at pins 5 and 6 (EXT_VCO_INP and EXT_VCO_INN,
respectively).
Digital Interface
A three-wire SPI provides mode and bias control, and control of
the PLL. The serial interface consists of three signals: the bus
clock (CLK), latch enable (LE), and the serial data line (DATA).
A write data stream consists of 25 bits:
Bits[15:0] provide the 16-bit data block.
Bits[20:16] provide the register address.
Bits[24:21] provide the device address (the SKY73208-11 is
0110b).
A timing diagram for the SPI write cycle is shown in Figure 3.
CLK
DATA
A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LE
Figure 3. SPI Write Cycles
A8 A7
S1930
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
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November 5, 2015 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201317F