SP574B Datasheet, PDF (5/15 Pages) Sipex Corporation – 12-Bit Sampling A/D Converters

PIN ASSIGNMENTS…
PIN FUNCTION
PIN FUNCTION
1
V_LOGIC
28
STS
2
12/8
27
DB₁₁(MSB)
3
CS
26
DB₁₀
4
A₀
25
DB₉
5
R/C
24
DB₈
6
CE
23
DB₇
7
V_CC
22
DB₆
8
REF OUT
21
DB₅
9
ANA GND(AC)
20
DB₄
10
REF IN
19
DB₃
11
N/C*
18
DB₂
12
BIP OFF
17
DB₁
13
10V_IN
16
DB₀(LSB)
14
20V_IN
15
DIG. GND
*This pin is not connected inside the device so it can
be tied to –15V, ground, or left floating.
FEATURES…
The SPx74B Series feature standard bipolar
and unipolar input ranges of 10V and 20V. Input
ranges are controlled by a bipolar offset pin and
laser-trimmed for specified linearity, gain and
offset accuracy. Power requirements are +5V
and +12V to +15V with a maximum dissipation
of 150mW at the specified voltages. Conversion
times of 8µs, 10µs, 15µs and 25µs are available,
as are units with 10, 25 or 50ppm/°C tempera-
ture coefficients for flexible matching to spe-
cific application requirements.
The SPx74B Series are available in nine prod-
uct grades for each conversion time. The –J
and –K models are specified over 0˚C to +
70˚C commercial temperature range; the –A
and –B models are specified over the –40˚C
to +85˚C industrial temperature range; the –S
and –T models are specified over the –55˚C to
+125˚C military temperature range. Package
options include 28–pin CDIP, 28–pin plastic
DIP (both narrow and wide), 28-pin PLCC
and 28–pin SOIC.
CIRCUIT OPERATION…
The SPx74B are complete monolithic capacitor
DAC–based 12–bit analog-to-digital convert-
ers with integral voltage reference, comparator,
successive–approximation register (SAR),
sample–and–hold, clock, output buffers and
control circuitry. The high level of integration
of the SPx74B Series means they require few
external components.
When the control section of the SPx74B initiates
a conversion command, the clock is enabled and
the successive–approximation register is reset to
all zeros. Once the conversion cycle begins, it can
not be stopped or restarted and data is not available
from the output buffers. The SAR, timed by the
clock, sequences through the conversion cycle and
returns an end–of–convert flag to the control sec-
tion of the ADC. The clock is then disabled by the
control section, the output status goes low, and the
control section is enabled to allow the data to be
read by external command.
The internal SPx74B 12–bit CDAC is sequenced
by the SAR starting from the MSB to the LSB at
the beginning of the conversion cycle to provide
an output voltage from the CDAC that is equal
to the input signal voltage (which is divided by
the input voltage divider network). The com-
parator determines whether the addition of each
successively–weighted bit voltage causes the
CDAC output voltage summation to be greater
or less than the input voltage; if the sum is less,
the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12–
bit binary code which accurately represents the
input signal to within ±¹â„₂ LSB.
The internal reference provides the voltage refer-
ence to the CDAC with excellent stability over
temperature and time. The reference is trimmed
to 10.00 Volts ±1% and can supply up to 2mA to
an external load in addition to that required to
drive the reference input resistor (1mA) and
offset resistor (1mA) when operating with ±15V
supplies. If the SPx74B is used with ±12V
supplies, or if external current must be supplied
over the full temperature range, an external
buffer amplifier is recommended. Any external
load on the SPx74B reference must remain
constant during conversion.
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
5
© Copyright 2000 Sipex Corporation