SP574B Datasheet, PDF (12/15 Pages) Sipex Corporation – 12-Bit Sampling A/D Converters

READ MODE TIMING
CE
CS
R/C
A0
STS
DB11–
DB0
tSSR
tSRR
tHSR
tHRR
tSAR
tHAR
HIGH
IMPEDANCE
tDD
DATA
VALID
tHD
tHL
CHARACTERISTICS
Typical @ 25˚C, V = +15V or +12V, V = +5V, V = 0V, unless otherwise specified.
CC
LOGIC
EE
PARAMETER
t_DD Access Time From CE²
t_HD Data Valid After CE Low²
t_HL Output Float Delay²
t_SSR CS to CE Setup
t_SRR R/C to CE Setup
t_SAR A₀ to CE Setup
t_HSR CS Valid After CE Low
t_HRR R/C High After CE Low
t_HAR A₀ Valid After CE Low
t_HS STS Delay After Data Valid
MIN.
25
50
0
50
0
0
50
300
TYP.
MAX.
150
150
0
0
0
50
1000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Parameters guaranteed by design and sample tested.
2. Parameters 100% tested @ 25˚C on special orders.
Figure 7. Read Mode Timing
CONDITIONS
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
12
© Copyright 2000 Sipex Corporation