SP706REN-L Datasheet, PDF (3/18 Pages) Sipex Corporation – Low Power Microprocessor Supervisory Circuits

SPECIFICATIONS
V_CC = 4.75V to 5.50V for SP705/707/813L,813M, V_CC = 4.50V to 5.50V for SP706/708, T_A = T_MIN to T_MAX, unless otherwise noted, typical at 25^oC.
PARAMETER
MIN. TYP. MAX. UNITS CONDITIONS
WDO Output Voltage
MR Pull-Up Current
V_CC-1.5
0.40
100 250 600
V
I_SOURCE=800µA
I_SINK=3.2mA
µA MR = 0V
MR Pulse Width, t_MR
150
ns
MR Input Threshold
LOW
HIGH
2.0
0.8
V
MR to Reset Out Delay, t_MD
250
ns Note 2
PFI Input Threshold
1.20 1.25 1.30
V
V_CC = 5V
PFI Input Current
-25.00 0.01 25.00 nA
PFO Output Voltage
V_CC-1.5
V
I_SOURCE = 800µA
0.4
I_SINK = 3.2mA
Note 1: The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA.
Note 2: Applies to both RESET in the SP705-SP708 and RESET in the SP707/708/813L/813M.
DIP and SOIC
µSOIC
MR ¹
VCC 2
GND 3
PFI 4
SP705
SP706
SP813L
SP813M
8 WDO
7 RESET / RESET*
6 WDI
5 PFO
RESET / RESET* ¹
WDO 2
MR 3
VCC 4
SP705
SP706
SP813L
SP813M
8 WDI
7 PFO
6 PFI
5 GND
MR ¹
VCC 2
GND 3
PFI 4
SP707
SP708
8 RESET
7 RESET
6 N.C.
5 PFO
Figure 1. Pinouts
* SP813L/M only
RESET ¹
RESET 2
MR 3
VCC 4
SP707
SP708
8 N.C.
7 PFO
6 PFI
5 GND
* SP813L/M only
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
3
© Copyright 2000 Sipex Corporation