SP706REN-L Datasheet, PDF (10/18 Pages) Sipex Corporation – Low Power Microprocessor Supervisory Circuits

tWP
+5V
WDI _0V
+5V
WDO _0V
+5V
RESET* _0V
+5V
RESET* _0V
tWD
tWD
tWD
tRS
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms
Typically, WDO will be connected to the
non-maskable interrupt input (NMI) of a µP.
When V_CC drops below the reset threshold,
WDO will go LOW whether or not the watch-
dog timer has timed out. Normally this would
trigger an NMI but RESET goes LOW simulta-
neously, and thus overrides the NMI.
If WDI is left unconnected, WDO can be used as
a low-line output. Since floating WDI disables
the internal timer, WDO goes LOW only when
V_CC falls below the reset threshold, thus func-
tioning as a low-line output.
+5V
VRT
VRT
VCC
0V
+5V
WDO
0V
+5V
RESET
0V
tRS
tRS
MR*
+5V
0V
*externally driven LOW
tMD
tMR
Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse
of the RESET Waveform Shown.
SP705DS/09
SP705 Low Power Microprocessor Supervisory Circuits
10
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