SP505 Datasheet, PDF (22/35 Pages) Sipex Corporation – WAN Multi-Mode Serial Transceiver

All receivers include a fail-safe feature that
outputs a logic "1" when the receiver inputs are
open. The differential receivers allocated for
data and clock signals (RxD, RxC, and SCT)
have advanced fail-safe that outputs a logic "1"
when the inputs are either open, shorted, or
terminated. Other discrete or integrated imple-
mentations require external pull-up and pull-
down resistors to define the receiver output
state. For single-ended V.28 receivers, there are
internal 5kΩ pull-down resistors on the inputs
which produces a logic high ("1") at the receiver
outputs. The single-ended V.10 receivers pro-
duce a logic LOW ("0") on the output when the
inputs are open. This is due to an internal pull-
up device connected to the input. The differen-
tial receivers have the same internal pull-up
device on the non-inverting input which pro-
duces a logic HIGH ("1") at the receiver output,
representing an "OFF" state to the HDLC con-
troller. The three differential receivers when
configured in V.35 mode (RxD, RxC & SCT)
will also include fail-safe even when the internal
termination resistor network is connected and
the inputs are either shorted or floating.
Decoder
The SP505 has the ability to change the inter-
face mode of the drivers or receivers via a 4–bit
switch. The decoder for the drivers and receiv-
ers can be latched through a control pin.
The control word can be latched either high or
low to write the appropriate code into the SP505.
The codes shown in Tables 1 and 2 are the only
specified, valid modes for the SP505. Unde-
fined codes may represent other interface modes
not specified (consult the factory for more infor-
mation). The drivers and receivers are con-
trolled with the data bits labeled DEC₃–DEC₀.
All of the drivers outputs and receiver outputs
can be put into tri-state mode by writing 0000 to
the driver decode switch. All internal termina-
tion networks are switched off during this mode.
Individual tri-state capability is possible for all
drivers through each driver's own enable control
input. The SCT receiver also contains an indi-
vidual enable input. When this control pin is
disabled (logic "0"), the V.11 and V.35 input
termination is deactivated. The 0000 decoder
word will override the enable control line for the
one receiver (SCT).
The SP505 contains internal loopback capabili-
ties for self-diagnostic tests. Loopback is en-
abled through the decoder. To initiate single-
ended mode loopback, the decoder word is 1010.
To initiate differential mode loopback, the de-
coder word is 1011. The minimum transmission
rates into the SP505 under loopback conditions
are 120kbps for single-ended mode and 5Mbps
for differential mode. The driver outputs are tri-
stated and the receiver inputs are disabled dur-
ing loopback. The receiver input impedance
during loopback is approximately 10kΩ.
The SP505 is equipped with a latch control for
the four (4) decoder bits. The latch control pin
is pin 8 of the SP505. The latch control is active
low, a logic low on pin 8 will latch the decoder
signals. A logic "1" on pin 8 will force the latch
to be transparent to the user. A pulse width of at
least 30ns is required to latch the decoder for the
next mode. The resultant output is typically
600ns after the latch control pin is toggled
assuming that the decoder word is set.
NET1/2 & TBR2 European Compliancy
As with all of Sipex's previous multi-protocol
serial transceiver ICs, the drivers and receivers
have been designed to meet all the requirements
to NET1/2. The SP505 is internally tested to all
the NET1/2 physical layer testing parameters
and the ITU Series V specifications.
With the emergence of ETSI TBR2 (Technical
Basis for Regulation) document now in place as
an alternative for European compliancy, Sipex
has tested the SP505 to TBR2 specifications to
ensure "CE" approval for either testing method.
The SP505 was externally tested by TUV
Telecom Services, Division of TUV Rheinland,
and passed both NET1/2 and TBR2 require-
ments. Test reports (NET2/052101/98 for NET1/2 and CTR2/
05101/98 for TBR2) can be furnished upon request.
Please note that although the SP505 adheres to
NET1/2 testing; any complex or unusual con-
figuration should be double-checked to ensure
NET compliance. Consult factory for details.
Rev: A Date: 1/27/04
SP505 Multi–Mode Serial Transceiver
22
© Copyright 2004 Sipex Corporation