SP505 Datasheet, PDF (19/35 Pages) Sipex Corporation – WAN Multi-Mode Serial Transceiver

Phase 2 (±10V)
— V_SS transfer — Phase two of the clock con-
nects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to ground, and transfers the generated –l0V or
the generated –5V to C₃. Simultaneously, the
positive side of capacitor C ₁ is switched to +5V
and the negative side is connected to ground.
Phase 2 (±5V)
—insescwVtei_{SdtScth&oeVdVtCoDCDgtrocohrueancrdgheaarnsgdteoCrtah2–}geieCs—c_1ocnaCnp1ea⁺_{cctiiestodrret.ocCoCn23+}-.
The 5V charge from Phase 1 is now transferred
to the V_SS storage capacitor. V_SS receives a
continuous charge from either C₁ or C₂. With
the C1 capacitor charged to 5V, the cycle begins
again.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –5V in the negative
terminal of C₁, which
side of capacitor C₂.
is applied
Since C₂₊
to
is
the negative
at +5V, the
voltage
output,
Cpo₂₊^{teinsticaolnancercotsesdCt2}o
is l0V.
ground
For the
so that
5V
the
potential on C₂ is only +5V.
Phase 4
— V_DD transfer — The fourth phase of the
clock connects the negative terminal of C₂ to
ground and transfers the generated l0V or the
generated 5V across C₂ to C₄, the V_DD storage
capacitor. Again, simultaneously with this, the
positive side of capacitor C₁ is switched to +5V
and the negative side is connected to ground,
and the cycle begins again.
Since both V_DD and V_SS are separately gener-
ated from V_CC in a no–load condition, V_DD and
aVp^Sp^SrowaicllhebsethsaytmgmeneetrriactaelV. ^O– flrdoemr
charge
V⁺ will
pump
show
a decrease in the magnitude of V^– compared to
V⁺ due to the inherent inefficiencies in the
design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be a minimum of 22µF with a 16V breakdown
rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V^– pins. The value of the external supply volt-
ages must be no greater than +l0.5V. The toler-
ance should be +5% from +10V. The current
drain for the supplies is used for RS-232 and RS-
423 drivers. For the RS-232 driver, the current
requirement will be 3.5mA per driver. The RS-
423 driver worst case current drain will be
11mA per driver. Power sequencing is required
for the SP505. The supplies must be sequenced
accordingly: +10V, +5V and –10V. It is impor-
tant to prevent V_SS from starting up before V_CC
or V_DD.
V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–10V
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 47. Charge Pump Phase 2 for +10V.
V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–5V
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 48. Charge Pump Phase 2 for +5V.
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 49. Charge Pump Phase 3.
V_CC = +5V
+
C_{1 –}
+10V
+
C_{2 –}
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 50. Charge Pump Phase 4.
Rev: A Date: 1/27/04
SP505 Multi–Mode Serial Transceiver
19
© Copyright 2004 Sipex Corporation