SP43503 Datasheet, PDF (7/10 Pages) SIPAT Co,Ltd – SP43503

SP43503
Product Specification
Figure 15. Serial Timing Diagram
Bits can either be set to logic high or logic low
D[0], D[1] and D[7] must be set to logic low
DI[6:2]
P/S
SI
CLK
T_DISU
T_PSSU
D[0]
T_SISU
T_SIH
LE
D[1]
T_CLKL
D[2]
D[3]
D[4]
D[5]
T_CLKH
D[6]
DO[6:0]
D[7]
T_DIH
T_PSIH
T_LESU
T_LEPW
T_PD
VALID
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
DI[6:2]
LE
DO[6:2]
T_PSSU
VALID
T_DISU
T_PSIH
T_DIH
T_LEPW
VALID
T_DIPD
T_PD
Table 10. Serial Interface AC Characteristics
V_DD = 3.3 or 5.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK
TCLKH
TCLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
-
10 MHz
30
-
ns
30
-
ns
TLESU
Last serial clock rising edge
setup time to Latch Enable
rising edge
10
-
ns
TLEPW Latch Enable min. pulse width 30
-
ns
TSISU Serial data setup time
10
-
ns
TSIH
Serial data hold time
10
-
ns
TDISU Parallel data setup time
100
-
ns
TDIH Parallel data hold time
100
-
ns
TASU Address setup time
100
-
ns
TAH
Address hold time
100
-
ns
TPSSU Parallel/Serial setup time
100
-
ns
TPSH Parallel/Serial hold time
100
-
ns
TPD
Digital register delay (internal)
-
10 ns
Table 11. Parallel and Direct Interface AC
Characteristics
V_DD = 3.3 or 5.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
TLEPW
Latch Enable minimum
pulse width
30
-
ns
TDISU
Parallel data setup time
100 -
ns
TDIH
Parallel data hold time
100 -
ns
TPSSU
Parallel/Serial setup time
100 -
ns
TPSIH
TPD
TDIPD
Parallel/Serial hold time
100 -
ns
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
-
10 ns
-
5
ns
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