SI8442BA-D-IS1 Datasheet, PDF (7/38 Pages) Silicon image – LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR

Si8440/41/42/45
Table 3. Electrical Characteristics (Continued)
(V_DD1 = 5 V ±10%, V_DD2 = 5 V ±10%, T_A = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
Si844xBx
Maximum Data Rate
0
—
150 Mbps
Minimum Pulse Width
—
—
6.0
ns
Propagation Delay
t_PHL, t_PLH See Figure 2
3.0
6.0
9.5
ns
Pulse Width Distortion
PWD
See Figure 2
—
1.5
2.5
ns
|t_PLH - t_PHL|
Propagation Delay Skew²
t_PSK(P-P)
—
2.0
3.0
ns
Channel-Channel Skew
t_PSK
—
0.5
1.8
ns
All Models
Output Rise Time
t_r
C_L = 15 pF
—
3.8
5.0
ns
See Figure 2
Output Fall Time
t_f
C_L = 15 pF
—
2.8
3.7
ns
See Figure 2
Common Mode Transient
CMTI
V_I = V_DD or 0 V
—
Immunity
25
— kV/µs
Enable to Data Valid³
t_en1
See Figure 1
—
5.0
8.0
ns
Enable to Data Tri-State³
t_en2
See Figure 1
—
7.0
9.2
ns
Start-up Time^3,4
t_SU
—
15
40
µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
7