SI8442BA-D-IS1 Datasheet, PDF (10/38 Pages) Silicon image – LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR

Si8440/41/42/45
Table 4. Electrical Characteristics (Continued)
(V_DD1 = 3.3 V ±10%, V_DD2 = 3.3 V ±10%, T_A = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V_DD1
V_DD2
—
3.6
5.4
mA
—
4.0
5.6
Si8441Bx
V_DD1
V_DD2
—
3.7
5.5
mA
—
4.1
5.7
Si8442Bx
V_DD1
V_DD2
—
4.2
5.9
mA
—
4.2
5.9
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V_DD1
V_DD2
Si8441Bx
V_DD1
V_DD2
Si8442Bx
V_DD1
V_DD2
—
—
—
—
—
—
Timing Characteristics
3.6
5.5
mA
14
17.5
6.4
8.0
mA
11.4
14.5
8.6
10.8 mA
8.6
10.8
Si844xAx
Maximum Data Rate
0
—
1.0 Mbps
Minimum Pulse Width
—
—
250
ns
Propagation Delay
t_PHL,t_PLH See Figure 2
—
—
35
ns
Pulse Width Distortion
|t_PLH - t_PHL|
Propagation Delay Skew²
PWD
See Figure 2
—
t_PSK(P-P)
—
—
25
ns
—
40
ns
Channel-Channel Skew
t_PSK
—
—
35
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t_PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.5