SI5013-D-GM Datasheet, PDF(9/26 Page) Silicon Laboratories – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

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SI5013-D-GM Datasheet, PDF (9/26 Pages) Silicon Laboratories – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

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Si5013

Table 4. AC Characteristics (PLL Characteristics)

(VDD = 3.3 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Jitter Tolerance

(OC-12 Mode)*

JTOL(PP)

f = 30 Hz

f = 300 Hz

f = 25 kHz

f = 250 kHz

0.4

Jitter Tolerance

(OC-3 Mode)*

JTOL(PP)

f = 30 Hz

f = 300 Hz

f = 6.5 kHz

f = 65 kHz

0.4

RMS Jitter Generation*

JGEN(rms) with no jitter on serial data â

Peak-to-Peak Jitter Generation*

JGEN(PP) with no jitter on serial data

Jitter Transfer Bandwidth*

JBW

OC-12 Mode

Jitter Transfer Peaking*

Acquisition TimeâOC-12

(Reference clock applied)

OC-3 Mode

TAQ

After falling edge of

PWRDN/CAL

From the return of valid

data

2.3

0.03

1.5

UIPP

4.0 mUI

mUI

500 kHz

130 kHz

0.1

Âµs

Acquisition TimeâOC-12

(Reference-less operation)

Reference Clock Range

TAQ

After falling edge of

4.0

PWRDN/CAL

From the return of valid

data

See "4.4. Operation

Without an External Ref-

erence" on page 12.

155.5

77.76

19.44

MHz

Input Reference Clock Frequency

Tolerance

CTOL

â500

500 ppm

Frequency Difference at which

Receive PLL goes out of Lock

(REFCLK compared to the divided

down VCO clock)

Â±650

ppm

*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 â 1 data pattern.

Rev. 1.6

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