SI5013-D-GM Datasheet, PDF (23/26 Pages) Silicon Laboratories – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
8. Package Outline
Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the
illustration. For a pad layout recommendation please contact Silicon Laboratories.
Figure 16. 28-Lead Quad Flat No-Lead (QFN)
Table 9. Package Diagram Dimensions
Controlling Dimension: mm
Symbol
Millimeters
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
5.00 BSC
D2
2.95
3.10
3.25
e
0.50 BSC
E
5.00 BSC
E2
2.95
3.10
3.25
L
0.50
0.60
0.70
θ
0°
—
12°
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1. 1.All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VHHD-1.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.6
23