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SI5013-D-GM Datasheet, PDF (8/26 Pages) Silicon Laboratories – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER | |||
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Si5013
Table 3. AC Characteristics (Clock and Data)
(VDD = 3.3 V ±5%, TA = â40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Clock Rate
fCLK
Rate Sel = 1
Rate Sel = 0
Output Rise TimeâOC-12
tR
Output Fall TimeâOC-12
tF
Output Clock Duty Cycleâ
OC-12/3
Figure 3
Figure 3
Clock to Data Delay
OC-12
OC-3
tCr-D
Figure 2
Clock to Data Delay
OC-12
OC-3
tCf-D
Figure 2
Input Return Loss
100 kHzâ622 MHz
Slicing Level Offset
(relative to the internally set
input common mode voltage)
Loss-of-Signal Range*
(peak-to-peak differential)
VSLICE SLICE_LVL = 750 mV to 2.25 V
VLOS
LOS_LVL = 1.50 to 2.50 V
Loss-of-Signal Response Time tLOS
Figure 5 on page 6
*Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL â 1.50)/25.
616
â
675 MHz
154
â
158
â
125
155
ps
â
125
155
ps
47
50
53 % of
UI
800 860
940
ps
4000 4100 4200
0
35
70
ps
800 850 1000
â15
â
â
dB
See Figure 8 on page 14.
0
â
40
mV
8
20
25
µs
8
Rev. 1.6
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