SI5367 Datasheet, PDF (8/18 Pages) Silicon Laboratories – μP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5367
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
5, 6, 15, 27, 32,
42, 62, 63, 76,
79, 81, 84, 86,
89, 91, 94, 96,
99, 100
7, 8, 14, 16, 18,
19, 21, 26, 28,
31, 33, 36, 38,
41, 43, 46, 64,
65
Pin Name
V_DD
GND
I/O Signal Level
Description
Vdd
Supply V_DD.
The device operates from a 1.8 or 2.5 V supply. Bypass
capacitors should be associated with the following V_DD
pins:
Pins
Bypass Cap
5, 6
0.1 µF
15
0.1 µF
27
0.1 µF
62, 63
0.1 µF
76, 79
1.0 µF
81, 84
0.1 µF
86, 89
0.1 µF
91, 94
0.1 µF
96, 99, 100 0.1 µF
GND
Supply
Ground.
This pin must be connected to system ground. Minimize
the ground path impedance for optimal performance.
9
C1B
O LVCMOS CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if
CK1_BAD_PIN = 1 and is tristated if CK1_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O LVCMOS CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if
CK2_BAD_PIN = 1 and is tristated if CK2_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
11
C3B
O LVCMOS CKIN3 Invalid Indicator.
This pin performs the CK3_BAD function if
CK3_BAD_PIN = 1 and is tristated if CK3_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
8
Preliminary Rev. 0.3