SI5367 Datasheet, PDF (2/18 Pages) Silicon Laboratories – μP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5367
Table 1. Performance Specifications
(V_DD = 1.8 or 2.5 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature Range
T_A
Supply Voltage
V_DD
–40
25
85
ºC
2.25
2.5
2.75
V
1.62
1.8
1.98
V
Supply Current
I_DD
f_OUT = 622.08 MHz
All CKOUTs enabled
—
394
435
mA
LVPECL format output
Only CKOUT1 enabled
—
253
284
mA
f_OUT = 19.44 MHz
All CKOUTs enabled
CMOS format output
—
278
321
mA
Only CKOUT1 enabled
—
229
261
mA
Tristate/Sleep Mode
—
TBD
TBD
mA
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5)
CK_F
CK_OF
Input frequency and clock
multiplication ratio determined
by programming device PLL
dividers. Consult Silicon Labo-
ratories configuration software
DSPLLsim or Any-Rate Preci-
sion Clock Family Reference
Manual at www.silabs.com/tim-
ing to determine PLL divider
settings for a given input fre-
quency/clock multiplication
ratio combination.
10
10
970
1213
—
707.35 MHz
—
945 MHz
—
1134
—
1417
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing CKN_DPP
Common Mode Voltage CKN_VCM
1.8 V ±10%
2.5 V ±10%
0.25
—
0.9
—
1.0
—
1.9
V_PP
1.4
V
1.7
V
Rise/Fall Time
Duty Cycle
CKN_TRF
CKN_DC
20–80%
Whichever is less
—
—
11
ns
40
—
60
%
50
—
ns
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
Common Mode
V_OCM
Differential Output Swing V_OD
LVPECL
100 Ω load
line-to-line
V_DD –
—
V_DD –
V
1.42
1.25
1.1
—
1.9
V
Single Ended Output
V_SE
Swing
0.5
—
0.93
V
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.3