SI5367 Datasheet, PDF (16/18 Pages) Silicon Laboratories – μP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5367
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Updated “2. Pin Descriptions: Si5367”.
Changed FSOUT (pins 87 and 88) to CLKOUT5.
Changed FS_ALIGN (pin 21) control pin to GND.
Changed pin 16 to ground.
Revision 0.2 to Revision 0.3
Removed references to latency control, INC, and
DEC pins.
Updated block diagram on page 1.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated “2. Pin Descriptions: Si5367”.
Changed font of register names to underlined italics.
Updated "3. Ordering Guide" on page 12.
Added “5. Recommended PCB Layout”.
16
Preliminary Rev. 0.3