SI52131-A11A Datasheet, PDF (8/19 Pages) Silicon Laboratories – No termination resistors required

Si52131-A11A
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
(
Ce1
+
1
Cs1
+
Ci1
+
Ce2
+
1
Cs2
+
Ci2
)
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
2.2. OE Pin Function
The OE pin is an active low input used to enable and disable the output clock. To enable the output clock, the OE
pin needs to be logic low and the I²C output enable bit needs to be logic high. By default, the OE pin is set to a logic
low and the I²C output enable bit is set to a logic high. There are two methods to disable the output clock: the OE
pin is pulled to a logic high or the I²C output enable bit is set to a logic low. The OE pin is required to be driven at all
times even though it has an internal 100 k resistor.
2.3. OE Assertion
The OE pin is an active low input used for synchronous stopping and starting the respective output clock while the
rest of the clock generator continues to function. The assertion of the OE function is achieved by pulling the OE pin
low and the I²C output enable bit high, which causes the respective stopped output to resume normal operation.
No short or stretched clock pulses are produced when the clocks resume. The maximum latency from the assertion
to active outputs is no more than two to six output clock cycles.
2.4. OE Deassertion
The OE function is de-asserted by pulling the pin high, or setting the I²C output enable bit to a logic low. The
corresponding output is stopped and the final output state is driven low.
2.5. SS[1:0] Pins Function
SS1 and SS0 are active inputs used to change the frequency and/or to enable –0.5% down spread on all DIFF
outputs. When sampled high or low, the appropriate selection of frequency and spread from Table 5 is applied on
all differential outputs. These inputs have an internal pull-down though a 100 k resistor. The default state is
SS[1:0] = 00, corresponding to 100 MHz outputs with spread spectrum disabled.
Table 5. SS0 & SS1 Frequency/Spread Selection
SS1
SS0
0
0
0
1
1
0
1
1
Differential
Frequency
100 MHz
100 MHz
125 MHz
200 MHz
Differential
Spread
Spread Off
–0.50%
Spread Off
Spread Off
8
Rev 1.0