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SI515 Datasheet, PDF (8/22 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR | |||
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Si515
Table 6. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = â40 to +85 oC; Output Format = LVDS
Parameter
Period Jitter
(RMS)
Period Jitter
(Pk-Pk)
Phase Jitter
(RMS)
Symbol
JPRMS
JPPKPK
Test Condition
10k samples1
10k samples1
Min
Typ
Max
Unit
â
â
2.1
ps
â
â
18
ps
ÏJ
1.875 MHz to 20 MHz integration
â
0.25
0.55
ps
bandwidth2 (brickwall)
Phase Noise,
156.25 MHz
12 kHz to 20 MHz integration band-
â
width2 (brickwall)
ÏN
100 Hz
â
1 kHz
â
0.8
1.1
ps
â72
â
dBc/Hz
â93
â
dBc/Hz
10 kHz
â
â114
â
dBc/Hz
100 kHz
â
â123
â
dBc/Hz
Spurious
SPR
1 MHz
LVPECL output, 156.25 MHz,
offset>10 kHz
â
â136
â
dBc/Hz
â
â75
â
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
8
Rev. 1.0
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