SI515 Datasheet, PDF (7/22 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR

Si515
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = LVPECL
Parameter
Period Jitter (RMS)
Period Jitter (PK-PK)
Phase Jitter (RMS)
Symbol
Test Condition
Min Typ Max
J_PRMS
10 k samples¹
—
—
1.3
J_PPKPK
10 k samples¹
—
—
11
12 kHz to 20 MHz² (brickwall)
—
0.9
1.3
φJ
1.875 MHz to 20 MHz² (brickwall)
—
0.25
0.5
Unit
ps
ps
ps
ps
Phase Noise, 155.52 MHz
100 Hz offset
—
–71
— dBc/Hz
1 kHz offset
—
–93
— dBc/Hz
φN
10 kHz offset
— –113 — dBc/Hz
100 kHz offset
— –124 — dBc/Hz
1 MHz offset
— –136 — dBc/Hz
Additive RMS Jitter Due to
External Power Supply
Noise³
J_PSRR
100 kHz sinusoidal noise
200 kHz sinusoidal noise
500 kHz sinusoidal noise
—
4.0
—
ps
—
3.5
—
ps
—
3.5
—
ps
1 MHz sinusoidal noise
—
3.5
—
ps
Spurious Performance
SPR
F_O = 156.25 MHz,
Offset > 10 kHz
—
–75
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mV_PP).
Rev. 1.0
7