SI515 Datasheet, PDF (6/22 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR

Si515
Table 4. Output Clock Levels and Symmetry
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
Symbol Test Condition
Min
CMOS Output Logic High
V_OH
CMOS Output Logic Low
V_OL
CMOS Output Logic High
Drive
I_OH
3.3 V
2.5 V
0.85 x V_DD
—
–8
–6
CMOS Output Logic Low
3.3 V
8
Drive
I_OL
2.5 V
6
CMOS Output Rise/Fall Time
(20 to 80% V_DD)
T_R/T_F
0.1 to 125 MHz,
C_L = 15 pF
0.1 to 212.5 MHz,
C_L = no load
—
—
LVPECL/HCSL Output
Rise/Fall Time
T_R/T_F
—
(20 to 80% V_DD)
LVDS Output Rise/Fall Time
(20 to 80% V_DD)
T_R/T_F
—
LVPECL Output Common
Mode
V_OC
50  to V_DD – 2 V,
single-ended
—
LVPECL Output Swing
V_O
50  to V_DD – 2 V,
single-ended
0.55
LVDS Output Common Mode _VOC
100  line-line,
V_DD = 3.3/2.5 V
1.13
LVDS Output Swing
V_O
Single-ended 100 
differential termination
0.25
HCSL Output Common Mode V_OC
50 to ground
0.35
HCSL Output Swing
V_O
Single-ended
0.58
Duty Cycle
DC
48
Typ
—
—
—
—
—
—
0.8
0.6
—
—
V_DD –
1.4 V
0.8
1.23
0.38
0.38
0.73
50
Max
—
0.15 x V_DD
—
—
—
—
Unit
V
V
mA
mA
mA
mA
1.2
ns
0.9
ns
565
ps
800
—
0.90
1.33
0.42
0.42
0.85
52
ps
V
V_PPSE
V
V_PPSE
V
V_PPSE
%
6
Rev. 1.0