SI552 Datasheet, PDF (7/8 Pages) Silicon Laboratories – DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Si552
4. Ordering Information
The Si552 was designed to support a variety of options including frequency, tuning slope, output format, and V_DD.
Specific device configurations are programmed into the Si552 at time of shipment. A unique part number
associated with these options and frequencies will be assigned. The Si552 Dual Frequency VCXO is provided in
an industry-standard, 7x5 package.
Part numbers for the Si552 Dual Frequency VCXO are determined by following configuration tables. Silicon Labs
provides a Windows-based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO
to access this tool and for further ordering instructions.
552
X
X
XXXXXX
B
X
R
552 VCXO
Product Family
1^st Option Code
VDD Output Format
A 3.3 LVPECL
B 3.3 LVDS
C 3.3 CMOS
D 3.3 CML
E 2.5 LVPECL
F 2.5 LVDS
G 2.5 CMOS
H 2.5 CML
J 1.8 CMOS
K 1.8 CML
Notes:
CMOS available to 160 MHz.
Tape & Reel Packaging
Operating Temp Range (°C)
G
-40 to +85°C
Part Revision Letter
Frequency Designator Code
Two unique frequencies can be specified within the following bands of frequencies:
10 to 945 MHz
970 to 1134 MHz
1213 to 1417 MHz
A six digit code will be assigned by SiLabs for the specified combination of frequencies .
2^nd Option Code (VCXO)
Temp Stability Tuning Slope
(ppm, max, ±) (Kv,ppm/V , typ ,) APR(typ)@3.3V APR(typ )@2.5V APR(typ )@1.8V
A 100
180
185
115
50
B 100
90
38
Note 3
Note 3
C 50
180
235
165
100
D 50
90
85
50
20
E 20
45
40
25
Note 3
Notes:
1. Pull range (±) = 0.5 x V_DD x tuning slope .
2. Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
=0.5xVDD x tuning slope – stability – 10 ppm
3. Combination not available .
APR is the ability of a VCXO to track a signal over the product lifetime . Thus, a VCXO
with an APR of 50 ppm is able to lock to a clock with 50 ppm stability, for a 15 year life.
Preliminary Rev. 0.2
7