SI552 Datasheet, PDF (2/8 Pages) Silicon Laboratories – DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Si552
1. Electrical Specifications
Parameter
Nominal Frequency
LVDS/CML/LVPECL
CMOS
Initial Accuracy
Temperature Stability
Linearity
BSL
Incremental
Tuning Slope (kV) from 10 to
90% of V_DD
Modulation Bandwidth
V_C Input Impedance
Absolute Pull Range (APR)
Aging
Symmetry
RMS Jitter for F_OUT > 500 MHz
Kv = 180 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
Kv = 45, 90 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
Table 1. Si552 Electrical Specifications
Min
10
10
–1.5
–20
–50
–100
–5
–10
Typ
Max
Frequency
—
945
—
160
—
1.5
—
+20
—
+50
—
+100
±1
+5
±5
+10
—
180
—
—
90
—
—
45
—
—
10
—
500
—
—
—
See Notes
—
—
—
±10
Outputs
45
—
55
Units
Notes
MHz
Specified at time of order by P/N.
Also available in bands from
970 to 1134 MHz and 1213 to
1417 MHz.
ppm ^{Measured at +25 °C at time of ship-}
ping and at V_C = V_DD/2.
Selectable option by P/N. See
ppm Section 4. "Ordering Information" on
page 7. Measured at V_C = V_DD/2.
BSL determined from deviation from
best straight line fit with V_C ranging
% from 10 to 90% of V_DD. Incremental
slope determined with V_C ranging
from 10 to 90% of V_DD.
Positive slope; selectable option by
ppm/V P/N. See Section 4. "Ordering Infor-
mation" on page 7.
kHz
kΩ
— ^{See Section 4. "Ordering Information"}
on page 7.
ppm ^{Projected frequency drift over 15 year}
life.
LVPECL: V_DD – 1.3 V (differential)
% _{LVDS: 1.25 V (differential)}
CMOS: V_DD/2
—
0.42
—
—
0.34
—
F_OUT > 500 MHz
ps _{Differential Modes:}
LVPECL/LVDS/CML
—
0.28
—
—
0.31
—
2
Preliminary Rev. 0.2