SI552 Datasheet, PDF (3/8 Pages) Silicon Laboratories – DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Si552
Table 1. Si552 Electrical Specifications (Continued)
Parameter
Min
RMS Jitter for F_OUT of 125 to
500 MHz
12 kHz to 20 MHz
—
50 kHz to 80 MHz
—
Period Jitter for F_OUT < 160 MHz
Peak-to-Peak
—
RMS
—
Typ
0.61
0.52
7
2
Max
Units
Notes
125 < F_OUT < 500 MHz
—
ps _{Differential Modes:}
—
LVPECL/LVDS/CML
—
ps ^{Any output}
—
N = 1000 cycles
LVPECL Output Option
mid-level
swing (diff)
V_DD – 1.42
1.1
—
—
V_DD – 1.25
1.9
V
V_PP
50 Ω to V_DD – 2.0 V
swing (single-ended)
0.5
—
0.93
V_PP
LVDS Output Option
mid-level
swing (diff)
1.125
1.2
1.275
V R_term = 100 Ω (differential)
0.5
0.7
0.9
V_PP
CML Output Option
mid-level
swing
—
V_DD – 0.36
—
0.35
0.425
0.5
V _{Rterm = 100 Ω (differential)}
V_PP
CMOS Output Option
V_OH
V_OL
Rise/Fall time
0.8xV_DD
—
—
—
—
1
V_DD
V C_L = 15 pF
0.4
350
ps CML/LVPECL/LVDS at 20% / 80%
—
ns _CMOS
Inputs
Voltage
3.3 V option
2.5 V option
1.8 V option
2.97
2.25
3.3
2.5
3.63
2.75
V _{Optional parameter specified by P/N}
1.71
1.8
1.89
Supply Current
—
90
—
mA
Control Voltage (V_C)
Frequency Select
V_IL
V_IH
0
—
0
—
0.75 x V_DD
—
V_DD
V _{Tuning range for control voltage}
0.5
V “0” selects F1
V_DD
“1” selects F2
Parameter
Supply Voltage
Storage Temperature
Table 2. Absolute Maximum Ratings
Symbol
V_DD
T_S
Rating
–0.5 to +3.8
–55 to +125
Units
V
°C
Preliminary Rev. 0.2
3