SI512 Datasheet, PDF (7/20 Pages) Silicon Laboratories – DUAL FREQUENCY CRYSTAL OSCILLATOR

Si512/513
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Period Jitter JPRMS
10k samples¹
—
(RMS)
Period Jitter JPPKPK
10k samples¹
—
(Pk-Pk)
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
bandwidth² (brickwall)
12 kHz to 20 MHz integration band-
—
width (brickwall)²
Phase Noise,
φN
100 Hz
—
156.25 MHz
1 kHz
—
10 kHz
—
100 kHz
—
1 MHz
—
Additive RMS
JPSR
10 kHz sinusoidal noise
—
Jitter Due to
External Power
Supply Noise³
100 kHz sinusoidal noise
—
500 kHz sinusoidal noise
—
1 MHz sinusoidal noise
—
Spurious
SPR
LVPECL output, 156.25 MHz,
—
offset > 10 kHz
Typ
—
—
0.31
0.8
–86
–109
–116
–123
–136
3.0
3.5
3.5
3.5
–75
Max
Units
1.3
ps
11
ps
0.5
ps
1.0
ps
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
ps
—
ps
—
ps
—
ps
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
Rev. 1.0
7