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SI512 Datasheet, PDF (5/20 Pages) Silicon Laboratories – DUAL FREQUENCY CRYSTAL OSCILLATOR | |||
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Si512/513
Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = â40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Nominal Frequency
FO
CMOS, Dual CMOS
0.1
â
212.5 MHz
FO
LVDS/LVPECL/HCSL
0.1
â
250
MHz
Total Stability*
Frequency Stability Grade C
â30
+30
ppm
Frequency Stability Grade B
â50
+50
ppm
Frequency Stability Grade A
â100
+100 ppm
Temperature Stability
Frequency Stability Grade C
â20
+20
ppm
Frequency Stability Grade B
â25
+25
ppm
Frequency Stability Grade A
â50
+50
ppm
Startup Time
TSU
Minimum VDD to output
â
â
10
ms
frequency (FO) within specification
Disable Time
TD
FO ï³ï 10 MHz
â
â
5
µs
FO < 10 MHz
â
â
40
µs
Enable Time
TE
FO ï³ï 10 MHz
â
â
20
µs
FO < 10 MHz
â
â
60
µs
Settling Time after FS
Change
tFRQ
â
â
10
ms
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40 °C.
Rev. 1.0
5
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