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SI512 Datasheet, PDF (6/20 Pages) Silicon Laboratories – DUAL FREQUENCY CRYSTAL OSCILLATOR | |||
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Si512/513
Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = â40 to +85 oC
Parameter
Symbol
Test Condition
Min
CMOS Output Logic
VOH
High
CMOS Output Logic
VOL
Low
CMOS Output Logic
IOH
High Drive
3.3 V
2.5 V
0.85 x VDD
â
â8
â6
1.8 V
â4
CMOS Output Logic
IOL
3.3 V
8
Low Drive
2.5 V
6
1.8 V
4
CMOS Output Rise/Fall TR/TF
0.1 to 125 MHz,
â
Time
CL = 15 pF
(20 to 80% VDD)
0.1 to 212.5 MHz,
â
CL = no load
LVPECL/HCSL Output TR/TF
â
Rise/Fall Time
(20 to 80% VDD)
LVDS Output Rise/Fall TR/TF
â
Time
(20 to 80% VDD)
LVPECL Output
VOC
50 ï to VDD â 2 V,
â
Common Mode
single-ended
LVPECL Output Swing
VO
50 ï to VDD â 2 V,
0.55
single-ended
LVDS Output Common
Mode
VOC 100 ï line-line, VDD = 3.3/2.5 V
100 ï line-line, VDD = 1.8 V
1.13
0.83
LVDS Output Swing
VO Single-ended, 100 ï differential 0.25
termination
HCSL Output Common VOC
50 ïï to ground
0.35
Mode
HCSL Output Swing
VO
Single-ended
0.58
Duty Cycle
DC
All Output Formats
48
Typ
â
â
â
â
â
â
â
â
0.8
0.6
â
â
VDD â
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
Max Units
â
V
0.15 x VDD V
â
mA
â
mA
â
mA
â
mA
â
mA
â
mA
1.2
ns
0.9
ns
565
ps
800
ps
â
V
0.90
1.33
1.00
0.45
0.42
0.85
52
VPPSE
V
V
VPPSE
V
VPPSE
%
6
Rev. 1.0
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