ISL29033 Datasheet, PDF (7/15 Pages) Intersil Corporation – Simple output code directly proportional to lux

ISL29033
transaction begins with the master asserting a start condition
(SDA falling while SCL remains high). The following byte is driven
by the master and includes the slave address and the read/write
bit. The receiving device is responsible for pulling SDA low during
the acknowledgment period. Every I²C transaction ends with the
master asserting a stop condition (SDA rising while SCL remains
high).
For more information about the I²C standard, consult the
Philips^™ I²C specification documents.
FIGURE 2. I²C TIMING DIAGRAM
I²C DATA
I²C SDA
IN
I²C SDA
OUT
I²C CLK
START
DEVICE ADDRESS W A REGISTER ADDRESS
STOP START DEVICE ADDRESS
A
DATA BYTE0
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
A6 A5 A4 A3 A2 A1 A0 W A
SDA DRIVEN BY ISL29033
SDA DRIVEN BY MASTER
A SDA DRIVEN BY MASTER A
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
12 3456 789123456 789
123 45 67 89123456789
FIGURE 3. I²C READ TIMING DIAGRAM SAMPLE
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FN7656.5
September 28, 2016