SI52112-B5 Datasheet, PDF (6/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR

Si52112-B5/B6
Table 3. AC Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Spread Range
Modulation Frequency
S_RNG
F_MOD
Down Spread, -B6 only
—
-B6 only
30
Enable/Disable and Set-up
Clock Stabilization from Power-
T_STABLE
—
up
Stopclock Set-up Time
T_SS
10.0
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Typ
–0.5
31.5
—
—
Max Unit
—
%
33 kHz
3
ms
—
ns
Table 4. Thermal Conditions
Parameter
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case (TDFN)
Dissipation, Junction to Case (TSSOP)
Dissipation, Junction to Ambient (TDFN)
Dissipation, Junction to Ambient (TSSOP)
Symbol
T_S
T_A
T_J
Ø_JC
Ø_JC
Ø_JA
Ø_JA
Test Condition
Non-functional
Functional
Functional
JEDEC (JESD 51)
JEDEC (JESD 51)
JEDEC (JESD 51)
JEDEC (JESD 51)
Min Typ Max Unit
–65 — 150 °C
–40
—
85 °C
—
— 150 °C
—
— 38.3 °C/W
—
— 37.0 °C/W
—
— 90.4 °C/W
—
— 124.0 °C/W
Table 5. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
ESD Protection (Human Body Model)
Flammability Rating
Symbol
Test Condition
Min Typ Max Unit
V_{DD_3.3V}
—
— 4.6 V
V_IN
Relative to V_SS
–0.5 —
4.6 V_DC
ESD_HBM JEDEC (JESD 22 - A114) 2000 —
—
V
UL-94
UL (Class)
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup. Power
supply sequencing is not required.
6
Rev 1.2