SI52112-B5 Datasheet, PDF (5/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR

Si52112-B5/B6
Table 3. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle-to-Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF Clocks
Duty Cycle
Skew
Output Frequency
Frequency Accuracy
Slew Rate
L_ACC
T_DC
T_R/T_F
T_CCJ
T_LTJ
V_IH
V_IL
I_IH
I_IL
T_DC
T_SKEW
F_OUT
F_ACC
t_r/f2
Measured at V_DD/2 differential —
Measured at V_DD/2
45
Measured between 0.2 V_DD and 0.5
0.8 V_DD
Measured at V_DD/2
—
Measured at V_DD/2
—
XIN/CLKIN pin
2
XIN/CLKIN pin
—
XIN/CLKIN pin, VIN = V_DD
—
XIN/CLKIN pin, 0 < VIN <0.8 –35
Measured at 0 V differential
45
Measured at 0 V differential
—
VDD = 3.3 V
—
All output clocks
—
Measured differentially from
0.6
±150 mV
Cycle-to-Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Common Clock
T_CCJ
Pk-Pk_GEN1
RMS_GEN2
RMS_GEN3
Measured at 0 V differential
—
PCIe Gen 1
—
10 kHz < F < 1.5 MHz
—
1.5 MHz < F < Nyquist
—
PLL BW of 2–4 or 2–5 MHz,
—
CDR = 10 MHz
PCIe Gen 3 Phase Jitter,
RMS_{GEN3_SRNS} PLL BW of 2–4 or 2–5 MHz,
—
Separate Reference No Spread,
CDR = 10 MHz
SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
RMS_GEN4
PLL BW of 2–4 or 2–5 MHz,
—
CDR = 10 MHz
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
V_OX
V_HIGH
V_LOW
300
—
–0.3
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Typ Max Unit
—
250 ppm
—
55
%
—
4.0 V/ns
—
250
ps
—
350
ps
— V_DD+0.3 V
—
0.8
V
—
35
µA
—
—
µA
—
55
%
—
60
ps
100
— MHz
—
100 ppm
—
4.0 V/ns
28
70
ps
24
86
ps
1.35
3.0
ps
1.4
3.1
ps
0.4
1.0
ps
0.28 0.71 ps
0.4
1.0
ps
—
550 mV
—
1.15
V
—
—
V
Rev 1.2
5