EFM32TG110 Datasheet, PDF (53/65 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

Figure 5.3. QFN24 PCB Stencil Design
a
...the world's most energy friendly microcontrollers
b
x
y
e
c
z
d
Table 5.3. QFN24 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
a
b
c
d
Dim. (mm)
0.60
0.25
0.65
5.00
Symbol
e
x
y
z
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.3 (p. 50) .
Dim. (mm)
5.00
1.00
1.00
0.50
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions. Place as many and as small as possible vias
underneath each of the solder patches under the ground pad.
2015-03-06 - EFM32TG110FXX - d0013_Rev1.40
53
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