EFM32TG110 Datasheet, PDF (35/65 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Symbol
Parameter
Condition
Min
Continuous Mode
f_DAC
DAC clock frequen-
cy
Sample/Hold Mode
Sample/Off Mode
CYC_DACCONV Clock cyckles per
conversion
t_DACCONV
t_DACSETTLE
SNR_DAC
Conversion time
Settling time
Signal to Noise Ra-
tio (SNR)
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
SNDR_DAC
Signal to Noise-
pulse Distortion Ra-
tio (SNDR)
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
SFDR_DAC
Spurious-Free
Dynamic
Range(SFDR)
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
V_DACOFFSET
DNL_DAC
Offset voltage
Differential non-lin-
earity
After calibration, single ended
V_DD= 3.0 V, V_DD reference
INL_DAC
Integral non-lineari- V_DD= 3.0 V, V_DD reference
ty
MC_DAC
No missing codes
Typ
2
Max
Unit
1000 kHz
250 kHz
250 kHz
2
µs
5
µs
58
dB
59
dB
57
dB
54
dB
62
dBc
56
dBc
2
mV
±1
LSB
±5
LSB
12
bits
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.16. OPAMP
Symbol
I_OPAMP
G_OL
Parameter
Condition
Min
OPA2 BIASPROG=0xF,
HALFBIAS=0x0, Unity Gain
Active Current
OPA2 BIASPROG=0x7,
HALFBIAS=0x1, Unity Gain
OPA2 BIASPROG=0x0,
HALFBIAS=0x1, Unity Gain
OPA2 BIASPROG=0xF,
HALFBIAS=0x0
Open Loop Gain
OPA2 BIASPROG=0x7,
HALFBIAS=0x1
OPA2 BIASPROG=0x0,
HALFBIAS=0x1
Typ
Max
Unit
350
405 µA
95
115 µA
13
17 µA
101
dB
98
dB
91
dB
2015-03-06 - EFM32TG110FXX - d0013_Rev1.40
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