EFR32MG1 Datasheet, PDF (51/94 Pages) Silicon Laboratories – Home and Building Automation and Security

4.1.20 USART SPI
SPI Master Timing
EFR32MG1 Mighty Gecko SoC with Integrated Serial Flash Data Sheet
Electrical Specifications
Table 4.33. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
SCLK period ^{1 2}
t_SCLK
2*
—
t_HFPERCLK
CS to MOSI ^{1 2}
t_{CS_MO}
0
—
SCLK to MOSI ^{1 2}
t_{SCLK_MO}
3
—
MISO setup time ^{1 2}
t_{SU_MI}
IOVDD = 2.3 V
IOVDD = 3.0 V
56
—
37
—
MISO hold time ^{1 2}
t_{H_MI}
6
—
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of V_DD (figure shows 50% of V_DD)
Max
Unit
—
ns
8
ns
20
ns
—
ns
—
ns
—
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_MO
tSCKL_MO
tSCLK
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 50