SI52142 Datasheet, PDF (5/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2 & GEN 3 CLOCK TWO OUTPUT GENERATOR WITH 25 MHZ REFERENCE CLOCK

Si52142
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Min
Crystal
Long-term Accuracy
L_ACC
Measured at VDD/2 differential
—
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
T_DC
T_R/T_F
T_CCJ
T_LTJ
V_IH
V_IL
I_IH
I_IL
Measured at VDD/2
47
Measured between 0.2 V_DD and 0.5
0.8 V_DD
Measured at VDD/2
—
Measured at VDD/2
—
XIN/CLKIN pin
2
XIN/CLKIN pin
—
XIN/CLKIN pin, VIN = VDD
—
XIN/CLKIN pin, 0 < VIN <0.8
–35
DIFF at 0.7 V
DIFF Duty Cycle
T_DC
Measured at 0 V differential
45
Any DIFF Clock Skew from the T_SKEW(win Measured at 0 V differential
—
earliest bank to the latest bank
dow)
DIFF Cycle to Cycle Jitter
T_CCJ
Measured at 0 V differential
—
Output PCIe Gen1 REFCLK RMS_GEN1 Includes PLL BW 1.5–22 MHz,
0
Phase Jitter
ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz with BER = 1E-12
Output PCIe Gen2 REFCLK RMS_GEN2 Includes PLL BW 8–16 MHz,
0
Phase Jitter
Jitter Peaking = 3 dB, ζ = 0.54,
Td=12 ns, Low Band,
F < 1.5 MHz
Output PCIe Gen2 REFCLK RMS_GEN2 Includes PLL BW 8–16 MHz, Jitter 0
Phase Jitter
Peaking = 3 dB, ζ = 0.54,
Td=12 ns, High Band,
1.5 MHz < F < Nyquist
Output Phase Jitter Impact— RMS_GEN3 Includes PLL BW 2 – 4 MHz,
0
PCIe Gen3
CDR = 10 MHz)
DIFF Long Term Accuracy
L_ACC
Measured at 0 V differential
—
DIFF Rising/Falling Slew Rate T_R / T_F
Measured differentially from
1
±150 mV
Voltage High
V_HIGH
—
Voltage Low
V_LOW
–0.3
Crossing Point Voltage at 0.7 V V_OX
300
Swing
Typ Max Unit
—
250 ppm
—
53
%
—
4.0 V/ns
—
250
ps
—
350
ps
— VDD+0.3 V
—
0.8
V
—
35
µA
—
—
µA
—
55
%
—
50
ps
35
50
ps
40
108
ps
2
3.0
ps
2
3.1
ps
0.5
1.0
ps
—
100 ppm
—
8
V/ns
—
1.15
V
—
—
V
—
550 mV
Preliminary 0.1
5