SI52142 Datasheet, PDF (17/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2 & GEN 3 CLOCK TWO OUTPUT GENERATOR WITH 25 MHZ REFERENCE CLOCK

Pin #
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24
25
Si52142
Table 8. Si52142 24-Pin QFN Descriptions (Continued)
Name
NC
VDD_DIFF
DIFF0
DIFF0
DIFF1
DIFF1
VDD_DIFF
OE_DIFF1
SCLK
SDATA
VDD_CORE
XOUT
XIN/CLKIN
VSS_CORE
Type
NC No Connect
Description
PWR 3.3 V power supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I SMBus compatible SCLOCK
I/O SMBus compatible SDATA
PWR 3.3 V power supply
O 25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
I 25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input
GND Ground
GND
GND Ground for bottom pad of the IC
Preliminary 0.1
17