SI52142 Datasheet, PDF (16/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2 & GEN 3 CLOCK TWO OUTPUT GENERATOR WITH 25 MHZ REFERENCE CLOCK

Si52142
5. Pin Descriptions: 24-Pin QFN
VDD_REF 1
REF 2
OE_REF¹ ₃
VSS_REF 4
OE_DIFF0¹ 5
VDD_DIFF 6
24 23 22 21 20 19
18 OE_DIFF1¹
17 ^VDD_DIFF
25
GND
16 _DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
7 8 9 10 11 12
Pin #
1
2
3
4
5
6
7
8
9
10
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Name
VDD_REF
REF
OE_REF
VSS_REF
OE_DIFF0
VDD_DIFF
SS0
SS1
NC
NC
Table 8. Si52142 24-Pin QFN Descriptions
Type
PWR 3.3 V Power Supply
Description
O, SE 3.3 V, 25 MHz crystal reference clock
I,PU 3.3 V input to disable REF Clock (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
GND Ground
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
PWR 3.3 V Power Supply
I, PD 3.3 V tolerant latch-input for enabling Frequency/ Spread selection on
DIFF0 and DIFF1 outputs. Refer to Table 1 on page 4 for SS[1:0] speci-
I, PD fications.
NC No Connect
NC No Connect
16
Preliminary 0.1