EFM32TG225 Datasheet, PDF (48/66 Pages) Silicon Laboratories – Configurable peripheral I/O locations

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Table 4.2. Alternate functionality overview
Alternate
LOCATION
Functionality 0
1
2
3
4
5
6
Description
ACMP0_CH0
PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1
PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2
PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3
PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4
PC4
Analog comparator ACMP0, channel 4.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0
PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1
PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2
PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3
PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH5
PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6
PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7
PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1
PE12
Clock Management Unit, clock output number 1.
DAC0_N1 /
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0 /
OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
PC0
PC1
PC2 PC3
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
DAC0_OUT1ALT /
OPAMP_OUT1ALT
PC13 PC14 PC15
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P0 /
OPAMP_P0
PC4
Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
DBG_SWCLK
PF0
PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has
a built-in pull down.
DBG_SWDIO
PF1
PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has
a built-in pull up.
DBG_SWO
PF2
PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
2015-03-06 - EFM32TG225FXX - d0205_Rev1.40
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