EFM32TG225 Datasheet, PDF (46/66 Pages) Silicon Laboratories – Configurable peripheral I/O locations

BGA48 Pin#
and Name
Pin Name
Analog
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Pin Alternate Functionality / Description
Timers
Communication
Other
A3
PE11
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
A4
PF5
PRS_CH2 #1
A5
PF3
PRS_CH0 #1
A6
PC14
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
LES_CH14 #0
A7
PC15
ACMP1_CH7
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0
DBG_SWO #1
B1
PA1
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
B2
PA0
TIM0_CC0 #0/1/4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
B3
PE10
TIM1_CC0 #1
US0_TX #0
BOOT_TX
B4
PF4
PRS_CH1 #1
B5
PF2
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
B6
PC11
ACMP1_CH3
US0_TX #2
LES_CH11 #0
B7
PC13
ACMP1_CH5
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
LES_CH13 #0
C1
PC0
ACMP0_CH0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5
US1_TX #0
I2C0_SDA #4
LES_CH0 #0
PRS_CH2 #0
C2
PA2
TIM0_CC2 #0/1
CMU_CLK0 #0
C3
VSS
Ground.
C4
IOVDD_5
Digital IO power supply 5.
C5
PF1
TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0/1
GPIO_EM4WU3
C6
PC9
ACMP1_CH1
US0_CLK #2
LES_CH9 #0
GPIO_EM4WU2
C7
PC10
ACMP1_CH2
US0_RX #2
LES_CH10 #0
D1
PC1
ACMP0_CH1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5
US1_RX #0
I2C0_SCL #4
LES_CH1 #0
PRS_CH3 #0
D2
PC3
ACMP0_CH3
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
LES_CH3 #0
D3
IOVDD_0
Digital IO power supply 0.
D5
PF0
TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0/1
D6
PC8
ACMP1_CH0
US0_CS #2
LES_CH8 #0
D7
DECOUPLE
Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLE is required at this pin.
E1
PC2
ACMP0_CH2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
LES_CH2 #0
E2
PC4
ACMP0_CH4
DAC0_P0 /
LETIM0_OUT0 #3
LES_CH4 #0
2015-03-06 - EFM32TG225FXX - d0205_Rev1.40
46
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