SI102X Datasheet, PDF (471/538 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

Si102x/3x
amble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false
detections may be tolerated. When antenna diversity is enabled a 20-bit preamble detection threshold is
recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter
preamble detection threshold may be used. Table 32.5 demonstrates the recommended preamble detec-
tion threshold and preamble length for various modes.
It is possible to use the transceiver in a raw mode without the requirement for a 010101... preamble. Con-
tact customer support for further details.
Table 32.5. Minimum Receiver Settling Time
Mode
(G)FSK AFC Disabled
(G)FSK AFC Enabled
(G)FSK AFC Disabled
+Antenna Diversity Enabled
(G)FSK AFC Enabled
+Antenna Diversity Enabled
OOK
OOK + Antenna Diversity
Enabled
Approximate
Receiver
Settling Time
1 byte
2 byte
Recommended Preamble Recommended Preamble
Length with 8-Bit
Length with 20-Bit
Detection Threshold
Detection Threshold
20 bits
32 bits
28 bits
40 bits
1 byte
—
64 bits
2 byte
2 byte
8 byte
—
3 byte
—
8 byte
4 byte
8 byte
Note: The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER.
They may be shortened when occasional packet errors are tolerable.
32.6.8. Invalid Preamble Detector
When scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in
the minimum amount of time. The preamble detector can output an invalid preamble detect signal. which
can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid
preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for
invalid preamble is defined as (inv_pre_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid pre-
amble detect signals are available in "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status
2.”
32.6.9. Synchronization Word Configuration
The synchronization word length for both TX and RX can be configured in Reg 33h, synclen[1:0]. The
expected or transmitted sync word can be configured from 1 to 4 bytes as defined below:
 synclen[1:0] = 00—Expected/Transmitted Synchronization Word (sync word) 3.
 synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2.
 synclen[1:0] = 10—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2,
followed by sync word 1.
 synclen[1:0] = 1—Send/Expect Synchronization Word 3 first, followed by sync word 2, followed by sync
word 1, followed by sync word 0.
The sync is transmitted or expected in the following sequence: sync 3sync 2sync 1sync 0. The sync
word values can be programmed in Registers 36h–39h. After preamble detection the part will search for
sync for a fixed period of time. If a sync is not recognized in this period then a timeout will occur and the
search for preamble will be re-initiated. The timeout period after preamble detections is defined as the
value programmed into the sync word length plus four additional bits.
Rev. 0.3
471