SI102X Datasheet, PDF (16/538 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

Si102x/3x
Figure 32.12. Packet Structure .............................................................................. 466
Figure 32.13. Multiple Packets in TX Packet Handler ........................................... 467
Figure 32.14. Required RX Packet Structure with Packet Handler Disabled ........ 467
Figure 32.15. Multiple Packets in RX Packet Handler ........................................... 468
Figure 32.16. Multiple Packets in RX with CRC or Header Error .......................... 468
Figure 32.17. Operation of Data Whitening, Manchester Encoding, 
and CRC ......................................................................................... 470
Figure 32.18. Manchester Coding Example .......................................................... 470
Figure 32.19. Header ............................................................................................. 472
Figure 32.20. POR Glitch Parameters ................................................................... 473
Figure 32.21. General Purpose ADC Architecture ................................................ 476
Figure 32.22. Temperature Ranges using ADC8 .................................................. 478
Figure 32.23. WUT Interrupt and WUT Operation ................................................. 481
Figure 32.24. Low Duty Cycle Mode ..................................................................... 482
Figure 32.25. RSSI Value vs. Input Power ............................................................ 484
Figure 32.26. Si1024 Split RF TX/RX Direct-Tie 
Reference Design—Schematic ....................................................... 485
Figure 32.27. Si1020 Switch Matching Reference Design—Schematic ................ 486
Figure 33.1. T0 Mode 0 Block Diagram ................................................................. 494
Figure 33.2. T0 Mode 2 Block Diagram ................................................................. 495
Figure 33.3. T0 Mode 3 Block Diagram ................................................................. 496
Figure 33.4. Timer 2 16-Bit Mode Block Diagram ................................................. 501
Figure 33.5. Timer 2 8-Bit Mode Block Diagram ................................................... 502
Figure 33.6. Timer 2 Capture Mode Block Diagram .............................................. 503
Figure 33.7. Timer 3 16-Bit Mode Block Diagram ................................................. 507
Figure 33.8. Timer 3 8-Bit Mode Block Diagram ................................................... 508
Figure 33.9. Timer 3 Capture Mode Block Diagram .............................................. 509
Figure 34.1. PCA Block Diagram ........................................................................... 513
Figure 34.2. PCA Counter/Timer Block Diagram ................................................... 515
Figure 34.3. PCA Interrupt Block Diagram ............................................................ 516
Figure 34.4. PCA Capture Mode Diagram ............................................................. 518
Figure 34.5. PCA Software Timer Mode Diagram ................................................. 519
Figure 34.6. PCA High-Speed Output Mode Diagram ........................................... 520
Figure 34.7. PCA Frequency Output Mode ........................................................... 521
Figure 34.8. PCA 8-Bit PWM Mode Diagram ........................................................ 522
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 523
Figure 34.10. PCA 16-Bit PWM Mode ................................................................... 524
Figure 34.11. PCA Module 5 with Watchdog Timer Enabled ................................ 525
Figure 35.1. Typical C2 Pin Sharing ...................................................................... 536
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Rev. 0.3