EZR32HG320 Datasheet, PDF (4/87 Pages) Silicon Laboratories – Consumer electronics

3. System Overview
EZR32HG320 Data Sheet
System Overview
3.1 Introduction
The EZR32HG320 Wireless MCUs are the latest in the Silicon Labs family of wireless MCUs delivering a high-performance, low-energy
wireless solution integrated into a small form factor package. By combining a high performance sub-GHz RF transceiver with an energy
efficient 32-bit ARM Cortex-M0+, the EZR32HG family provides designers with the ultimate in flexibility with a family of pin-compatible
parts that scale from 32 to 64 kB of flash and support Silicon Labs EZRadio or EZRadioPRO transceivers. The ultra-low power operat-
ing modes and fast wake-up times combined with the low transmit and receive power consumption of the sub-GHz radio result in a
solution optimized for low power and battery powered applications. For a complete feature set and in-depth information on the modules,
the reader is referred to the EZR32HG Reference Manual.
The EZR32HG320 block diagram is shown below.
Core and Memory
EZR32HG320 F64/F32
Clock Management
ARM Cortex™ M0+ processor
Flash
Program
Memory
RAM
Memory
Debug
Interface
w/ MTB
DMA
Controller
Energy Management
Voltage
Regulator
Voltage
Comparator
Brown-out
Detector
Power-on
Reset
Security
Hardware
AES
32-bit bus
Peripheral Reflex System
TX 18 mA
@ +10 dBm
Transceiver
142-1050
MHz
ASK, OOK
G(FSK)
4(G)FSK
Serial Interfaces
USART
I²C
RX 10 mA
Preamble
1 Mbps
SPI
Sense 6.0 mA
Low
SPI
Energy
USB
Antenna
Diversity
133 dBm
sensitivity
Low
Energy
UART™
I/O Ports
External
Interrupts
General
Purpose
I/O
Pin
Reset
Pin
Wakeup
Timers and Triggers
Timer/
Counter
Real Time
Counter
Pulse
Counter
Watchdog
Timer
Analog Interfaces
ADC
Current
DAC
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone MIPS/MHz. A Wake-up Interrupt
Controller handling interrupts triggered while the CPU is asleep is included as well. The EZR32 implementation of the Cortex-M0+ is
described in detail in ARM Cortex-M0+ Devices Generic User Guide.
3.1.2 Debugging Interface (DBG)
These devices include hardware debug support through a 2-pin serial-wire debug interface.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EZR32HG microcontroller. The flash memory is readable and
writable from both the Cortex-M0+ and DMA. The flash memory is divided into two blocks: the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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