AN865 Datasheet, PDF (4/7 Pages) Silicon Laboratories – APPLYING DUTY-CYCLE CONTROL TO SAVE POWER

AN865
Figure 3 shows the previous idea in a real-world example. Here, the circuit periodically transmits an identifying
code utilizing a 433 MHz SAW resonator transmitter. The duty-cycling clock provides the timing for the bursts by
enabling a logic pattern generator (possibly a fed-back, shift-register-based code generator) to feed the transmitter
with an OOK (on-off keyed) signal for transmission. As a bonus, the clock provides the transmitter with
approximately doubled voltage (3.3 V) during the clock’s “on time”, enabling the SAW resonator to transmit at a
reasonable transmit power level.
Capacitor C3 serves as the charge pump’s flying capacitor, with the lower side of the cap driven by Output A, which
is fundamentally the duty-cycler clock. The cap charges through Schottky diode D1 when the clock is low, and the
output rises to approximately 2 x V_IN (minus D1 diode drop) when the clock is high. Q3 clamps the bottom of C3 to
V_IN when the clock is high, completing a low-impedance, series-connected path of C2 and C3 as the double-
stacked bypass capacitor for the output. The values of C2 and C3 should be chosen to support the load and on-
time duration at OUT. C2 = C3 = 100 µF was chosen for this design, which provided a minimum of 3 V during the
“on time” of 500 µs for a 25 mA load. Q4 provides an optional load cutoff; however, the SAW resonator transmitter
does not need to be disconnected in this way since it draws virtually no current when the logic pattern generator
provides a “zero” level.
Logic gates U2 and U3 add some timing adjustments to the duty-cycling clock. Output B is not enabled until Output
A goes high. Output B falls before Output A, thus ensuring break-before-make timing for Q3. Additionally, this
timing ensures that the pattern generator does not start until the SAW resonator transmitter has had some time to
settle with its boosted supply voltage and that it stops transmission before the boosted voltage is removed from the
transmitter. “AUP” family logic is utilized for low supply currents over temperature.
Radio Burst
VOUT (no optional
cutoff switch)
˜3.5V
1.8V
BURST ON
Figure 4. . “On-Time” Waveforms (for the Circuit in Figure 3)
The “no load” currents measured in the circuit show almost no overhead increase with the added boost circuitry,
and the loaded currents reflect the 3.5 mA average load current drawn by the transmitter during the 500 µs burst
period.
Table 2. No-Load Currents
I_IN (with Tx load of 3.3 V/3.5 mA during 500 µs)
4.1 µA
I_IN (No Load)
0.58 µA
4
Rev. 1.0