AN865 Datasheet, PDF (2/7 Pages) Silicon Laboratories – APPLYING DUTY-CYCLE CONTROL TO SAVE POWER

AN865
The timing is set up as follows: First, the upper (V_UPTHR) and lower (V_LWTHR) hysteretic trip thresholds are set with
R1, R2, and R3:
V_UPTHR
=
V_B
A
T
T

--------------^R-----²--------------
R₂
+
-^R----¹----^-----^R-----³-
R₁ + R₃
-^R----²----^-----^R-----³-
V_LWTHR
=
V_B
A
TT

-------^R-----²----+-----^R----³--------
R₁
+
-^R----²----^-----^R-----³-
R₂ + R₃
Then, R4 can be chosen according to the desired off-time:
R₄
=
–-------------------^T----^o---^f--^f------------------
C₁

ln


V_{-V----LU---W-P---TT---H-H---RR--}
and R5 is chosen according to the desired on-time:
R₅
=
–--------------------------------------^T----^o---ⁿ--------------------------------------
C₁  ln _1 – ^V---_V--^U--_B-^P--_A--^T--_T-^H--_T--^R--–---–--_V--^V--_L--^L-_W--^W---_T--^T-_H--^H--_R--^R--_
Note that since V_UPTHR and V_LWTHR are just a scaling of V_BATT, neither T_ON nor T_OFF are dependent on V_BATT.
The TSM9119’s input bias currents of less than 2 nA (across temperature) enable the use of high-value resistors.
Use of 10 M resistors yielded less than 30 mV net offset referred to the comparator inputs. Many off-the-shelf
bipolar transistors can be substituted for Q1 and Q2; however, gold-doped discrete transistors (most 2N3904 and
2N3906 transistors are not gold-doped) should be avoided because gold doping increases leakage currents^*. All
capacitors should be ceramic for lowest leakage (generally limited by the case resistance). The circuit performs
well even at hot temperatures, where leakages typically increase. Using a capacitor with an NPO (COG) dielectric
improves frequency stability and further reduces dielectric absorption issues (dielectric absorption can cause the
capacitor to “remember” its charge when discharged through Q1; however, this is not meant to be a precision
timing circuit). Table 1 lists the currents measured for the duty-cycling clock shown.
*Note: See “Troubleshooting Analog Circuits,” p.66, by Bob Pease.
Table 1. Duty Cycling Clock Currents
V_BATT
1.8
2.5
3.3
5
I_BATT
502 nA
580 nA
670 nA
890 nA
T_ON
1.02 ms
1.02 ms
1.02 ms
1.05 ms
T_OFF
1.04 s
1.04 s
1.04 s
1.04 s
What are some uses for this clock? Perhaps the most obvious use is for the oscillator to serve as a clock to
periodically wake a microcontroller. While most microcontrollers have built-in interrupt timers, not all have such low
supply currents. The microcontroller can be set to a deep sleep mode and woken up by the duty-cycling clock to
periodically check system status.
This “duty-cycler” might further enable current savings by periodically powering a simple measurement, the results
of which, in turn, wake a microcontroller. Thus, the microcontroller only wakes upon a result when it needs to take
action, not simply whenever it is interrupted by the timer.
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Rev. 1.0