AN865 Datasheet, PDF (1/7 Pages) Silicon Laboratories – APPLYING DUTY-CYCLE CONTROL TO SAVE POWER

AN865
APPLYING DUTY-CYCLE CONTROL TO SAVE POWER
1. Introduction
Shutting down inactive circuitry can save substantial power; however, this kind of power management assumes
there is an actively managing “brain” (typically a microcontroller) that knows when to turn things on and off. In
extremely low-power systems running at sub-microamp levels, it may instead be desirable to let the microcontroller
remain in a deep sleep mode and use a simple, ultra-low-power clock to wake circuitry at periodic intervals. While
many microcontrollers have such timers, a simple analog clock built from an extremely low-power comparator can
run at lower power, removing the need for powering up from the interrupt timer and, in some cases, eliminating the
need for a microcontroller altogether. In addition, the analog clock may operate from low voltages (as low as 1 V
from a single cell) and provide a periodic boosted voltage without the need for a separate regulator.
The circuits shown here are based on a simple relaxation oscillator utilizing a very low-power comparator. Running
at around 500 nA, the oscillator is configured as a very low-duty cycle clock used to duty-cycle power to circuitry in
small bursts. Periodically, the clock goes “high”; circuitry is enabled, and power is delivered. Most of the time, the
clock stays low and the circuitry is not powered, leaving only the oscillator running as an “always on” duty-cycling
clock. In Figure 1, a very low-power analog comparator (TSM9119) provides a very low-power clock for applying
duty-cycling control.
Figure 1. Basic Oscillator Design
Rev. 1.0 1/15
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AN865