SI590 Datasheet, PDF (3/12 Pages) Silicon Laboratories – 1 ps MAX JITTER CRYSTAL OSCILLATOR

Si590/591
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option¹
LVDS Output Option²
Symbol
V_O
V_OD
V_SE
V_O
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
V_DD – 1.42
1.1
0.55
1.125
Typ
—
—
—
1.20
Max Units
V_DD – 1.25 V
1.9
V_PP
0.95
V_PP
1.275
V
V_OD
swing (diff)
0.5
0.7
0.9
V_PP
CML Output Option²
V_O
mid-level
—
V_DD – 0.75
—
V
V_OD
CMOS Output Option³
V_OH
V_OL
swing (diff)
0.70
0.8 x V_DD
—
0.95
—
—
1.20
V_PP
V_DD
V
0.4
Rise/Fall time (20/80%)
t_R, t_F
LVPECL/LVDS/CML
—
—
350
ps
CMOS with C_L = 15 pF
—
2
—
ns
Symmetry (duty cycle)
SYM LVPECL: V_DD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
—
55
%
CMOS: V_DD/2
Notes:
1. 50  to V_DD – 2.0 V.
2. R_term = 100  (differential).
3. C_L = 15 pF. Sinking or sourcing 12 mA for V_DD = 3.3 V, 6 mA for V_DD = 2.5 V, 3 mA for V_DD = 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter
Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)¹
for 50 MHz < F_OUT < 525 MHz
(LVPECL/LVDS/CML)
Phase Jitter (RMS)²
for 50 MHz < F_OUT < 160 MHz
(CMOS)
_J
12 kHz to 20 MHz — 0.5 1.0 ps
_J
12 kHz to 20 MHz — 0.6 1.0 ps
Notes:
1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.
2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment.
3.3 V supply voltage option only.
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Period Jitter*
J_PER
RMS
Peak-to-Peak
—
—
3
ps
—
—
35
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Preliminary Rev. 0.25
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