SI4463 Datasheet, PDF (25/53 Pages) Silicon Laboratories – HIGH-PERFORMANCE

Si4463/61/60-C
4.2.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would
like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX FIFO mode, the data bytes stored in FIFO memory are “packaged” together with other fields and bytes of
information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync
word, and CRC checksum. In TX mode, the packet structure may be highly customized by enabling or disabling
individual fields; for example, it is possible to disable both the Preamble and Sync Word fields and to load the entire
packet structure into FIFO memory. For further information on the configuration of the FIFOs for a specific
application or packet size, see "6. Data Handling and Packet Handler" on page 38. In RX mode, the Packet
Handler must be enabled to allow storage of received data bytes into RX FIFO memory. The Packet Handler is
required to detect the Sync Word, and proper detection of the Sync Word is required to determine the start of the
Payload. All bytes after the Sync Word are stored in RX FIFO memory except the CRC checksum and (optionally)
the variable packet length byte(s). When the FIFO is being used in RX mode, all of the received data may still be
observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can be quite
useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX State
when either the PACKET_SENT or PACKET_RX interrupt occurs. The chip will return to the state programmed in
the argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or
RXVALID_STATE[3:0]. For example, the chip may be placed into READY mode after a TX packet by sending the
“START TX” command and by writing 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of
the contents of the FIFO, and the PACKET_SENT interrupt will occur. When this event occurs, the chip will return
to the READY state as defined by TXCOMPLETE_STATE[3:0] = 30h.
4.2.2.2. FIFO Direct Mode (Infinite Receive)
In some applications, there is a need to receive extremely long packets (greater than 40 kB) while relying on
preamble and sync word detection from the on-chip packet handler. In these cases, the packet length is unknown,
and the device will load the bits after the sync word into the RX FIFO forever. Other features, such as Data
Whitening, CRC, Manchester, etc., are supported in this mode, but CRC calculation is not because the end of
packet is unknown to the device. The RX data and clock are also available on GPIO pins. The host MCU will need
to reset the packet handler by issuing a START_RX to begin searching for a new packet.
4.2.2.3. Automatic TX Packet Repeat
In TX mode, there is an option to send the FIFO contents repeatedly with a user-defined number of times to repeat.
This is limited to the FIFO size, and the entire contents of the packet including preamble and sync word need to be
loaded into the TX FIFO. This is selectable via the START_TX API, and packets will be sent without any gaps
between them.
4.2.2.4. Direct Mode
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs entirely. In TX
Direct mode, the TX modulation data is applied to an input pin of the chip and processed in “real time” (i.e., not
stored in a register for transmission at a later time). Any of the GPIOs may be configured for use as the TX Data
input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK or OOK). To achieve direct mode, the desired GPIO pin
must be configured as a digital input by setting the GPIO_PIN_CFG API command = enumeration 0x04 in addition
to setting the MODEM_MOD_TYPE API property to source the TXDATA stream from that same GPIO pin. For
GFSK, “TX_DIRECT_MODE_TYPE” must be set to synchronous. For 2FSK or OOK, the type can be set to
asynchronous or synchronous. The MOD_SOURCE[1:0] field within the MODEM_MOD_TYPE property should be
set = 0x01h for all Direct mode configurations. In RX Direct mode, the RX Data and RX Clock can be programmed
for direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the
FIFO or packet handler functions of the RFIC.
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